`timescale 1ns / 1ps
module basic_2_sim1;
    reg D0,D1,S;
    wire Y;
    basic_2 b2(D0,D1,S,Y);
    initial
    begin
        D0=0;D1=0;S=0;
        fork
            repeat (5) #5 D0=~D0;
            repeat (5) #10 D1=~D1;
            repeat (5) #20 S=~S;
        join
    end
    
endmodule
